M.TECH I Semester Regular& Supplementary Examination, April 2012
DIGITAL IC DESIGN
(Common to VLSI Systems, VLSI System Design,VLSI&VLSID,Embedded System)
1.
(a) Give an intuitive perspective of the static CMOS inverter with relevant diagrams.
(b)Explain the dynamic behavior of the CMOS inverter to determine its performance?
2.
(a) Explain the logical effort of two-input NAND and NOR gates with neat circuit diagrams .
(b) Elaborate signal integrity issues in dynamic CMOS design?
3.
(a) Illustrate the method of logical effort for transistor sizing.
(b)Explain the concept of power consumption in CMOS gates.
4.
(a) Design and draw the circuit diagram of logarithmic shifter using CMOS logic.
(b) Give the design considerations of a 4-Mbit SRAM.also draw its CMOS logic diagram.
5.
(a) Draw and explain the static and dynamic characteristics of BICMOS logic diagram.
(b)Write notes on delay and power consumption in BICMOS logic Circuits.
6.
(a) What are CMOS based Design rules? Explain any one of them with relevant example.
(b) Write notes on mead Conway design rules for the silicon gate NMOS process.
7.
Define and explain in brief for the following related to basic logic circuit concepts in digital IC design.
(a)Sheet resistance
(b) Area capacitance.
(c)Drive large capacitive load.
8.
(a) Explain the design approach of carry-look adder with neat sketch.
(b) Explain Booth’s algorithm and its modified algorithm.